HD6473032F16 Datasheet, PDF (481/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 13 Serial Communication Interface
Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error
in asynchronous mode.
Bit 3: PER
0
Description
Receiving is in progress or has ended normally^*1
(Initial value)
[Clearing conditions]
• The chip is reset or enters standby mode.
• Software reads PER while it is set to 1, then writes 0.
1
A receive parity error occurred^*2
[Setting condition]
The number of 1s in receive data, including the parity bit, does not match the
even or odd parity setting of O/E in SMR.
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous
value.
2. When a parity error occurs the SCI transfers the receive data into RDR but does not set
the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted TDR did not contain new transmit data, so transmission has ended. The TEND flag is
a read-only bit and cannot be written.
Bit 2: TEND
0
1
Description
Transmission is in progress
[Clearing conditions]
• Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
• The DMAC writes data in TDR.
End of transmission
(Initial value)
[Setting conditions]
• The chip is reset or enters standby mode.
• The TE bit is cleared to 0 in SCR.
• TDRE is 1 when the last bit of a serial character is transmitted.
Rev. 3.00 Mar 21, 2006 page 451 of 814
REJ09B0302-0300