HD6473032F16 Datasheet, PDF(624/847 Page) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD6473032F16 Datasheet, PDF (624/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

◁

Section 18 ROM

18.8.3 Error Protection

In error protection, an error is detected when H8/3052BF runaway occurs during flash memory

programming/erasing*1, or operation is not performed in accordance with the program/erase

algorithm, and the program/erase operation is aborted. Aborting the program/erase operation

prevents damage to the flash memory due to overprogramming or overerasing.

If the H8/3052BF malfunctions during flash memory programming/erasing, the FLER bit is set to

1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and

EBR2 settings*3 are retained, but program mode or erase mode is aborted at the point at which the

error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1, P2, E1, or

E2 bit. However, PV1, PV2, EV1 and EV2 bit setting is enabled, and a transition can be made to

verify mode.*2

FLER bit setting conditions are as follows:

1. When the flash memory of the relevant address area is read during programming/erasing

(including vector read and instruction fetch)

2. Immediately after exception handling (excluding a reset) during programming/erasing

3. When a SLEEP instruction (including software standby) is executed during

programming/erasing

4. When the CPU releases the bus to the DMAC during programming/erasing

Error protection is released only by a power-on reset and in hardware standby mode.

Notes: 1. State in which the P1 bit or E1 bit in FLMCR1, or the P2 bit or E2 bit in FLMCR2, is

set to 1. Note that NMI input is disabled in this state.

2. It is possible to perform a program-verify operation on the 128 bytes being

programmed, or an erase-verify on the block being erased.

3. FLMCR1, FLMCR2, EBR1, and EBR2 can be written to. However, the registers are

initialized if a transition is made to software standby mode while in the error-protected

state.

Rev. 3.00 Mar 21, 2006 page 594 of 814

REJ09B0302-0300

▷