HD6473032F16 Datasheet, PDF (618/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 18 ROM
Write pulse application subroutine
Sub-Routine Write Pulse
WDT enable
Set PSU1 (2) in FLMCR1(2)
Wait (tspsu) µs
*7
Set P1 (2) bit in FLMCR1 (2)
Wait (tsp) µs
*5*7
Clear P1 (2) bit in FLMCR1 (2)
Wait (tcp) µs
*7
Start of programming
START
Set SWE1 (2) bit in FLMCR1 (2)
Wait (tsswe) µs
*7
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Store 128-byte program data in program
data area and reprogram data area
*4
n= 1
m= 0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
*1
Sub-Routine-Call
Write pulse
See Note 6 for pulse width
Clear PSU1 (2) bit in FLMCR1 (2)
Set PV1 (2) bit in FLMCR1 (2)
Wait (tcpsu) µs
*7
Disable WDT
End Sub
Wait (tspv) µs
*7
H'FF dummy write to verify address
Wait (tspvr) µs
*7
Read verify data
*2
n←n+1
Note 6: Write Pulse Width
Increment address
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
Write Time (tsp) µsec
30
30
30
30
30
30
200
200
200
200
200
200
200
998
200
999
200
1000
200
Note: Use a 10 µs write pulse for additional programming.
Write data =
NG
verify data?
OK
NG
6≥n?
OK
Additional-programming data computation
m= 1
Transfer additional-programming data to
additional-programming data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram data area *4
128-byte
NG
data verification completed?
OK
Clear PV1 (2) bit in FLMCR1 (2)
Wait (tcpv) µs
*7
6≥n?
NG
RAM
Program data storage
area (128 bytes)
OK
Successively write 128-byte data from additional-
programming data area in RAM to flash memory ^*1
Sub-Routine-Call
Write Pulse (Additional programming)
Reprogram
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
NG
m=0?
OK
Clear SWE1 (2) bit in FLMCR1 (2)
Wait (tcswe) µs
*7 _NG
n ≥ N?
OK
Clear SWE1 (2) bit in FLMCR1 (2)
Wait (tcswe) µs
*7
End of programming
Programming failure
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (W) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data and a 128-byte area for storing reprogram data must be provided in RAM.
The contents of the reprogram data area are modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs should be applied according to the progress of the programming operation. See Note 6 for the pulse widths. When writing of additional-
programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
7. The wait times and value of N are shown in section 21.2.5, Flash Memory.
Reprogram Data Computation Table
Original Data
(D)
Verify Data
(V)
Reprogram Data
(X)
0
0
1
0
1
0
1
0
1
1
1
1
Comments
Programming completed
Programming incomplete;
reprogram
Still in erased state; no action
Additional-Programming Data Computation Table
Reprogram Data Verify Data
Additional-
(X')
(V)
Programming Data (Y)
Comments
0
0
0
Additional programming
to be executed
0
1
1
Additional programming
not to be executed
1
0
1
1
1
Additional programming
not to be executed
1
Additional programming
not to be executed
Figure 18.12 Program/Program-Verify Flowchart (128-Byte Programming)
Rev. 3.00 Mar 21, 2006 page 588 of 814
REJ09B0302-0300