HD6473032F16 Datasheet, PDF (799/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

ADCR—A/D Control Register
Appendix B Internal I/O Register
H'E9
A/D
Bit
7
6
5
4
3
2
1
0
TRGE
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
0
Read/Write
R/W
—
—
—
—
—
—
—*
Trigger enable
0 A/D conversion cannot be externally triggered
1 A/D conversion starts at the fall of the external trigger signal (ADTRG)
Note: * Bit 0 must not be set to 1; in a write, 0 must always be written in this bit.
ABWCR—Bus Width Control Register
H'EC
Bus controller
Bit
7
ABW7
Initial ^{Mode 1,3,5,6 1}
value _{Mode 2,4,7 0}
Read/Write
R/W
6
ABW6
1
0
R/W
5
ABW5
1
0
R/W
4
ABW4
1
0
R/W
3
ABW3
1
0
R/W
2
ABW2
1
0
R/W
1
ABW1
1
0
R/W
0
ABW0
1
0
R/W
Area 7 to 0 bus width control
Bits 7 to 0
ABW7 to ABW0 Bus Width of Access Area
0
Areas 7 to 0 are 16-bit access areas
1
Areas 7 to 0 are 8-bit access areas
ASTCR—Access State Control Register
H'ED
Bus controller
Bit
Initial value
Read/Write
7
AST7
1
R/W
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
3
AST3
1
R/W
2
AST2
1
R/W
1
AST1
1
R/W
0
AST0
1
R/W
Area 7 to 0 access state control
Bits 7 to 0
AST7 to AST0 Number of States in Access Cycle
0
Areas 7 to 0 are two-state access areas
1
Areas 7 to 0 are three-state access areas
Rev. 3.00 Mar 21, 2006 page 769 of 814
REJ09B0302-0300