HD6473032F16 Datasheet, PDF (410/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when TCNT overflows from
H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 10.59 shows the timing.
φ
TCNT
Overflow
signal
OVF
H'FFFF
H'0000
OVI
Figure 10.59 Timing of Setting of OVF
10.5.2 Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 10.60 shows the timing.
TSR write cycle
T₁
T₂
T₃
φ
Address
TSR address
IMF, OVF
Figure 10.60 Timing of Clearing of Status Flags
Rev. 3.00 Mar 21, 2006 page 380 of 814
REJ09B0302-0300