HD6473032F16 Datasheet, PDF (379/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
• Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in
TIOR. Figure 10.25 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system
clocks for capture of both edges.
φ
Input-capture input
Internal input
capture signal
TCNT
N
GRA, GRB
N
Figure 10.25 Input Capture Signal Timing
Rev. 3.00 Mar 21, 2006 page 349 of 814
REJ09B0302-0300