HD6473032F16 Datasheet, PDF (31/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 1 Overview
Section 1 Overview
1.1 Overview
The H8/3052BF is a group of microcontrollers (MCUs) that integrate system supporting functions
together with an H8/300H CPU core having an original Renesas Technology architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory
access controller (DMAC), a refresh controller, and other facilities.
The H8/3052BF has 512 kbytes of ROM and 8 kbytes of RAM.
Seven MCU operating modes offer a choice of data bus width and address space size. The modes
(modes 1 to 7) include one single-chip mode and six expanded modes.
The H8/3052BF has an F-ZTAT™* version with on-chip flash memory that can be programmed
on-board.
Table 1.1 summarizes the features of the H8/3052BF.
Note: * F-ZTAT (Flexible–Zero Turn Around Time) is a trademark of Renesas Technology Corp.
Rev. 3.00 Mar 21, 2006 page 1 of 814
REJ09B0302-0300