HD6473032F16 Datasheet, PDF (172/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 6 Bus Controller
6.4 Usage Notes
6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM
A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is
connected to area 3. For details see section 7, Refresh Controller.
6.4.2 Register Write Timing
ABWCR, ASTCR, and WCER Write Timing: Data written to ABWCR, ASTCR, or WCER
takes effect starting from the next bus cycle. Figure 6.20 shows the timing when an instruction
fetched from area 0 changes area 0 from three-state access to two-state access.
φ
Address
bus
T₁
T₂
T₃
T₁
T₂
T₃
T₁
T₂
ASTCR address
3-state access to area 0
2-state access
to area 0
Figure 6.20 ASTCR Write Timing
Rev. 3.00 Mar 21, 2006 page 142 of 814
REJ09B0302-0300