HD6473032F16 Datasheet, PDF (369/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

On-chip data bus
H
CPU L
Bus interface
Section 10 16-Bit Integrated Timer Unit (ITU)
H
L
Module
data bus
TCNTH TCNTL
Figure 10.11 Access to Timer Counter (CPU Reads TCNT, Lower Byte)
10.3.2 8-Bit Accessible Registers
The registers other than the timer counters (TCNTS), general registers A and B (GRAs and
GRBs), and buffer registers A and B (BRAs and BRBs) are 8-bit registers. These registers are
linked to the CPU by an internal 8-bit data bus.
Figures 10.12 and 10.13 show examples of byte read and write access to a TCR.
If a word-size data transfer instruction is executed, two byte transfers are performed.
On-chip data bus
H
CPU L
Bus interface
H
L
Module
data bus
TCR
Figure 10.12 Access to Timer Counter (CPU Writes to TCR)
Rev. 3.00 Mar 21, 2006 page 339 of 814
REJ09B0302-0300