HD6473032F16 Datasheet, PDF (244/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 DMA Controller
Table 8.8 Register Functions in Repeat Mode
Register
23
MAR
Function
Activated by
SCI 0 Receive-
Data-Full
Interrupt
Other
Activation
Destination
address
0 _register
Source
address
register
Initial Setting
Destination or
source address
23
All 1s
7
0
IOAR
7
0
ETCRH
Source
address
register
Transfer
counter
Destination
address
register
Transfer
counter
Source or
destination
address
Number of
transfers
7
0
ETCRL
Hold transfer
count
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Hold transfer Number of
count
transfers
Operation
Incremented or
decremented at
each transfer
until H'0000,
then restored to
initial value
Held fixed
Decremented
once per
transfer until
H'0000 is
reached, then
reloaded from
ETCRL
Held fixed
In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer
count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from
ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID
bits in DTCR. Specifically, MAR is restored as follows:
MAR ← MAR – (–1)^DTID · 2^DTSZ · ETCRL
ETCRH and ETCRL should be initially set to the same value.
In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0,
if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No
CPU interrupt is requested.
Rev. 3.00 Mar 21, 2006 page 214 of 814
REJ09B0302-0300