HD6473032F16 Datasheet, PDF (83/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 2 CPU
Exception
sources
Reset
Interrupt
Trap instruction
External interrupts
Internal interrupts (from on-chip supporting modules)
Figure 2.11 Classification of Exception Sources
End of bus release
Bus request
End of bus
Program execution state
release
Bus
request
Exception
SLEEP
instruction
with SSBY = 0
Bus-released state
Sleep mode
End of
exception
handling
Exception-handling state
Interrupt
NMI, IRQ₀, IRQ ₁,
or IRQ ₂ interrupt
SLEEP instruction
with SSBY = 1
Software standby mode
RES = High
Reset state^*1
STBY = High, RES = Low
Hardware standby mode^*2
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2.12 State Transitions
Rev. 3.00 Mar 21, 2006 page 53 of 814
REJ09B0302-0300