HD6473032F16 Datasheet, PDF (133/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 5 Interrupt Controller
5.4.3 Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5.5 Interrupt Response Time
External Memory
No. Item
1
Interrupt priority
decision
2
Maximum number of
states until end of
current instruction
3
Saving PC and CCR
to stack
4
Vector fetch
5
Instruction prefetch^*2
6
Internal processing^*3
On-Chip
Memory
2^*1
1 to 23
4
4
4
4
8-Bit Bus
2 States 3 States
2^*1
2^*1
1 to 27
1 to 31^*4
8
12^*4
8
12^*4
8
12^*4
4
4
16-Bit Bus
2 States 3 States
2^*1
2^*1
1 to 23
1 to 25^*4
4
6^*4
4
6^*4
4
6^*4
4
4
Total
19 to 41
31 to 57 43 to 73
19 to 41 25 to 49
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the
interrupt service routine.
3. Internal processing after the interrupt is accepted and internal processing after prefetch.
4. The number of states increases if wait states are inserted in external memory access.
Rev. 3.00 Mar 21, 2006 page 103 of 814
REJ09B0302-0300