HD6473032F16 Datasheet, PDF (135/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 5 Interrupt Controller
5.5.2 Instructions that Inhibit Interrupts
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after
determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is
currently executing one of these interrupt-inhibiting instructions, however, when the instruction is
completed the CPU always continues by executing the next instruction.
5.5.3 Interrupts during EEPMOV Instruction Execution
The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.
When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the
transfer is completed, not even NMI.
When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at
a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.
Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
5.5.4 Notes on Use of External Interrupts
The specifications provide for the IRQnF flag to be cleared by first reading the flag while it is set
to 1, then writing 0 to it. However, there are cases in which the IRQnF flag is erroneously cleared,
preventing execution of interrupt exception handling, simply by writing 0 to the flag, without first
reading 1 from it. This occurs when the following conditions are fulfilled.
Setting Conditions
1. When using multiple external interrupts (IRQa, IRQb)
2. When different clearing methods are used for the IRQaF flag and IRQbF flag, with the IRQaF
flag cleared by writing 0 to it, and the IRQbF flag cleared by hardware.
3. IRQaF flag clears and bit operation command is being used for the IRQ status register (ISR) or
the ISR is being read in bytes; IRQaF flag’s bits clear and other bit values read in bits are
written in bytes.
Rev. 3.00 Mar 21, 2006 page 105 of 814
REJ09B0302-0300