HD6473032F16 Datasheet, PDF (412/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
10.6 Usage Notes
This section describes contention and other matters requiring special attention during ITU
operations.
Contention between TCNT Write and Clear: If a counter clear signal occurs in the T₃ state of a
TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure
10.61.
TCNT write cycle
T₁
T₂
T₃
φ
Address bus
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'0000
Figure 10.61 Contention between TCNT Write and Clear
Rev. 3.00 Mar 21, 2006 page 382 of 814
REJ09B0302-0300