HD6473032F16 Datasheet, PDF (843/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix H Differences from H8/3048F-ZTAT
Item
RAM emulation block
configuration
Refresh controller
DMAC registers
MAR0AR, MAR0BR,
MAR1AR, MAR1BR
H8/3048F-ZTAT
On-chip RAM
H8/3052B F-ZTAT
Flash memory On-chip RAM
Flash memory
H'EF10
H'F000
H'F1FF
H'00000
H'DF10
H'F000
H'00000
H'01000
H'02000
H'03000
H'1FFFF
H'1F000
H'04000
H'05000
H'1F200 H'EFFF
H'06000
H'1F400
H'07000
H'1F600
H'08000
H'1F800
H'FF0F
H'1FA00 _H'FF0F
H'1FC00
H'1FE00
H'1FFFF
H'7FFFF
In modes 1 to 6, DRAM or PSRAM can
be directly connected to area 3.
In modes 1, 2, 3, 4, and 6, DRAM or
PSRAM can be directly connected to
area 3.
Cannot be used in mode 5 (because flash
area overlaps area 3).
MAR0AR (H'FF20), MAR0BR (H'FF28), MAR0AR (H'FF20), MAR0BR (H'FF28),
MAR1AR (H'FF30), MAR1BR (H'FF38) MAR1AR (H'FF30), MAR1BR (H'FF38)
All bits are reserved; they always return 1 All bits are reserved; they return an
if read, and cannot be modified.
undefined value if read, and cannot be
modified.
A/D register ADCR
ADCR (H'FFE9)
Initial value: H'7F
Bit 7 only is readable/writable.
Other bits are reserved; they always
return 1 if read, and cannot be modified.
ADCR (H'FFE9)
Initial value: H'7E
Bit 7 only is readable/writable.
Bit 0 is reserved, and must not be set to 1.
Other bits are reserved; they always
return 1 if read, and cannot be modified.
WDT register RSTCSR
RSTCSR (H'FFAB)
Initial value: '3F
Bits 7 and 6 only are readable/writable.
Other bits are reserved; they always
return 1 if read, and cannot be modified.
RSTCSR (H'FFAB)
Initial value: '3F
Bit 7 only is readable/writable.
Bit 6 is reserved, and must not be set to 1.
Other bits are reserved; they always
return 1 if read, and cannot be modified.
Note: The H8/3052B F-ZTAT program/erase procedures are different from those of the
H8/3048F-ZTAT.
Rev. 3.00 Mar 21, 2006 page 813 of 814
REJ09B0302-0300