HD6473032F16 Datasheet, PDF (33/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 1 Overview
Feature
Bus controller
Refresh
controller
DMA controller
(DMAC)
Description
• Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Chip select output available for areas 0 to 7
• 8-bit access or 16-bit access selectable for each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
• Bus arbitration function
• DRAM refresh
 Directly connectable to 16-bit-wide DRAM
 CAS-before-RAS refresh
 Self-refresh mode selectable
• Pseudo-static RAM refresh
 Self-refresh mode selectable
• Usable as an interval timer
• Short address mode
 Maximum four channels available
 Selection of I/O mode, idle mode, or repeat mode
 Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from
SCI channel 0, or external requests
• Full address mode
 Maximum two channels available
 Selection of normal mode or block transfer mode
 Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, external requests, or auto-request
Rev. 3.00 Mar 21, 2006 page 3 of 814
REJ09B0302-0300