HD6473032F16 Datasheet, PDF (521/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 13 Serial Communication Interface
The receive margin in asynchronous mode can therefore be expressed as in equation (1).
M = (0.5 – ¹ ) – (L – 0.5) F – ^{D – 0.5} (1 + F) × 100% _{................... (1)}
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
M = {0.5 – 1/(2 × 16)} × 100%
= 46.875% ............................................................................................. (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Usage of DMAC: To have the DMAC read RDR, be sure to select the SCI
receive-data-full interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.
Restrictions on Usage of the Serial Clock: When transmitting data using the serial clock as an
external clock, after clearing SSR of TDRE, maintain the space between each frame of the lead of
the transmission clock (start-up edge) at five states or more (see Figure 13.22). This condition is
also needed for continuous transmission. If it is not fulfilled, operational error will occur.
SCK
t*
t*
TDRE
TXD
X0 X1 X2 X3 X4 X5 X6 X7 Y0 Y1 Y2 Y3
Continuous transmission
Note: ^* Ensure that t ≥ 5 states.
Figure 13.22 Serial Clock Transmission (Example)
Rev. 3.00 Mar 21, 2006 page 491 of 814
REJ09B0302-0300