HD6473032F16 Datasheet, PDF (247/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 DMA Controller
8.4.5 Normal Mode
In normal mode the A and B channels are combined. One byte or word is transferred per request.
A designated number of these transfers are executed. Addresses are specified in MARA and
MARB. Table 8.9 indicates the register functions in I/O mode.
Table 8.9 Register Functions in Normal Mode
Register
23
MARA
Function
Initial Setting
0 ^{Source address Source address}
register
23
MARB
0 ^Destination
Destination
address register address
15
0 ^{Transfer counter Number of}
transfers
ETCRA
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
Operation
Incremented or
decremented once per
transfer, or held fixed
Incremented or
decremented once per
transfer, or held fixed
Decremented once per
transfer
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred.
The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by
1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer
ends. If the DTIE bit is set, a CPU interrupt is requested at this time. The maximum transfer count
is 65,536, obtained by setting ETCRA to H'0000.
Figure 8.8 illustrates how normal mode operates.
Rev. 3.00 Mar 21, 2006 page 217 of 814
REJ09B0302-0300