HD6473032F16 Datasheet, PDF (237/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 DMA Controller
Normal Mode
• Auto-request
The DMAC is activated by register setup alone, and continues executing transfers until the
designated number of transfers have been completed. A CPU interrupt can be requested at
completion of the transfers. Both addresses are 24-bit addresses.
 Cycle-steal mode
The bus is released to another bus master after each byte or word is transferred.
 Burst mode
Unless requested by a higher-priority bus master, the bus is not released until the
designated number of transfers have been completed.
• External request
One byte or word is transferred per request. A designated number of these transfers are
executed. A CPU interrupt can be requested at completion of the designated number of
transfers. Both addresses are 24-bit addresses.
Block Transfer Mode: One block of a specified size is transferred per request. A designated
number of block transfers are executed. At the end of each block transfer, one address is restored
to its initial value. When the designated number of blocks have been transferred, a CPU interrupt
can be requested. Both addresses are 24-bit addresses.
Rev. 3.00 Mar 21, 2006 page 207 of 814
REJ09B0302-0300