HD6473032F16 Datasheet, PDF (458/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 12 Watchdog Timer
12.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable/writable*¹ register that monitors the state of the reset signal
generated by watchdog timer overflow.
Bit
7
6
5
4
3
2
1
0
WRST —
—
—
—
—
—
—
Initial value
0
0
1
1
1
1
1
1
Read/Write R/(W)^*2 —
—
—
—
—
—
—
Reserved bits
Reserved bit
Must not be set to 1^*3
Watchdog timer reset
Indicates that a reset signal has been generated
Bit 7 is initialized by input of a reset signal at the RES pin. It is not initialized by reset signals
generated by watchdog timer overflow.
Notes: 1. RSTCSR differs from other registers in being more difficult to write. For details see
section 12.2.4, Notes on Register Access.
2. Only 0 can be written in bit 7, to clear the flag.
3. Do not set bit 6 to 1.
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip
internally.
Bit 7: WRST
0
1
Description
[Clearing conditions]
• Cleared to 0 by reset signal input at RES pin
(Initial value)
• Cleared by reading WRST when WRST = 1, then writing 0 in WRST
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer
operation
Rev. 3.00 Mar 21, 2006 page 428 of 814
REJ09B0302-0300