HD6473032F16 Datasheet, PDF (449/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 11 Programmable Timing Pattern Controller
• H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and
G2CMS0 are set in TPCR to select compare match in the ITU channel set up in step 1 as the
output trigger. Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping
output. Output data H'95 is written in NDRB.
• The timer counter in this ITU channel is started. When compare match B occurs, outputs
change from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change
from 0 to 1 is delayed by the value of GRA). The IMFA interrupt service routine writes the
next output data (H'65) in NDRB.
• Four-phase complementary non-overlapping pulse output can be obtained by writing H'59,
H'56, H'95… at successive IMFA interrupts. If the DMAC is set for activation by this
interrupt, pulse output can be obtained without loading the CPU.
11.3.5 TPC Output Triggering by Input Capture
TPC output can be triggered by ITU input capture as well as by compare match. If GRA, and GRB
functions as an input capture register in the ITU channel selected in TPCR, TPC output will be
triggered by the input capture signal. Figure 11.8 shows the timing.
φ
TIOC pin
Input capture
signal
NDR
N
DR
M
N
Figure 11.8 TPC Output Triggering by Input Capture (Example)
Rev. 3.00 Mar 21, 2006 page 419 of 814
REJ09B0302-0300