HD6473032F16 Datasheet, PDF (155/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 6 Bus Controller
16-Bit, Three-State-Access Areas: Figures 6.6 to 6.8 show the timing of bus control signals for a
16-bit, three-state-access area. In these areas, the upper address bus (D₁₅ to D₈) is used to access
even addresses and the lower address bus (D₇ to D₀) is used to access odd addresses. Wait states
can be inserted.
Bus cycle
T₁
T₂
T₃
φ
Address bus
CS_n
Even external address in area n
AS
RD
Read
access
D₁₅ to D₈
D₇ to D ₀
HWR
Valid
Invalid
Write
access
LWR
D₁₅ to D₈
High
Valid
D₇ to D ₀
Note: n = 7 to 0
Undetermined data
Figure 6.6 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address)
Rev. 3.00 Mar 21, 2006 page 125 of 814
REJ09B0302-0300