HD6473032F16 Datasheet, PDF (547/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 14 Smart Card Interface
14.4 Usage Notes
When using the SCI as a smart card interface, note the following points.
Receive Data Sampling Timing in Smart Card Mode and Receive Margin: In smart card mode
the SCI operates on a base clock with 372 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the 186th base clock pulse. See figure 14.10.
372 clocks
186 clocks
0
185
371 0
185
Internal
base clock
Receive data
Start
(RxD)
bit
D0
371 0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 14.10 Receive Data Sampling Timing in Smart Card Mode
The receive margin can therefore be expressed as follows.
Receive margin in smart card mode:
M = 0.5 – ¹ – (L – 0.5) F – ^{D – 0.5} (1 + F) × 100%
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute deviation of clock frequency
Rev. 3.00 Mar 21, 2006 page 517 of 814
REJ09B0302-0300