HD6473032F16 Datasheet, PDF (360/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.
Bit 6: CCLR1
Bit 5: CCLR0
Description
0
0
TCNT is not cleared
(Initial value)
1
TCNT is cleared by GRA compare match or input
capture^*1
1
0
TCNT is cleared by GRB compare match or input
capture^*1
1
Synchronous clear: TCNT is cleared in synchronization
with other synchronized timers^*2
Notes: 1. TCNT is cleared by compare match when the general register functions as an output
compare register, and by input capture when the general register functions as an input
capture register.
2. Selected in TSNC.
Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges
when an external clock source is used.
Bit 4: CKEG1
0
1
Bit 3: CKEG0
0
1
—
Description
Count rising edges
Count falling edges
Count both edges
(Initial value)
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.
Phase counting takes precedence.
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Bit 2: TPSC2
0
1
Bit 1: TPSC1
0
1
0
1
Bit 0: TPSC0
0
1
0
1
0
1
0
1
Description
Internal clock: φ
(Initial value)
Internal clock: φ/2
Internal clock: φ/4
Internal clock: φ/8
External clock A: TCLKA input
External clock B: TCLKB input
External clock C: TCLKC input
External clock D: TCLKD input
Rev. 3.00 Mar 21, 2006 page 330 of 814
REJ09B0302-0300