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| HD6473032F16 Datasheet, PDF (151/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series | |||
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Section 6 Bus Controller
6.3.2 Chip Select Signals
For each of areas 7 to 0, the H8/3052BF can output a chip select signal (CS7 to CS0) that goes low
to indicate when the area is selected. Figure 6.3 shows the output timing of a CSn signal (n = 7 to
0).
Output of CS3 to CS0: Output of CS3 to CS0 is enabled or disabled in the data direction register
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS0 in the output state and
pins CS3 to CS1 in the input state. To output chip select signals CS3, to CS1 the corresponding
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
CS3 to CS0 in the input state. To output chip select signals CS3, to CS0 the corresponding DDR bits
must be set to 1. For details see section 9, I/O Ports.
Output of CS7 to CS4: Output of CS7 to CS4 is enabled or disabled in the chip select control
register (CSCR). A reset leaves pins CS7 to CS4 in the input state. To output chip select signals
CS7 to CS4, the corresponding CSCR bits must be set to 1. For details see section 9, I/O Ports.
Ï
Address
bus
CSn
External address in area n
Figure 6.3 CSn Output Timing (n = 7 to 0)
When the on-chip ROM, on-chip RAM, and on-chip registers are accessed, CS7 and CS0 remain
high. The CSn signals are decoded from the address signals. They can be used as chip select
signals for SRAM and other devices.
Rev. 3.00 Mar 21, 2006 page 121 of 814
REJ09B0302-0300
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