HD6473032F16 Datasheet, PDF (539/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 14 Smart Card Interface
The following equation calculates the bit rate register (BRR) setting from the system clock
frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.
φ
N=
1488 × 2^2n–1 × B
× 10⁶ – 1
Table 14.6 BRR Settings for Typical Bit Rate (bits/s) (when n = 0)
Bit/s
9600
7.1424
N Error
0 0.00
10.00
N Error
1 30.00
10.7136 13.00
N Error N Error
1 25.00 1 8.99
φ (MHz)
14.2848 16.00
N Error N Error
1 0.00 1 12.01
18.00
N Error
2 15.99
20.00
N Error
2 6.66
25.00
N Error
3 12.49
Table 14.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface)
φ (MHz)
Maximum Bit Rate (bits/s)
N
n
7.1424
9600
0
0
10
13441
0
0
10.7136
14400
0
0
13
17473
0
0
14.2848
19200
0
0
16
21505
0
0
18
24194
0
0
20
26882
0
0
25
33602
0
0
The bit rate error is calculated from the following equation.
Error (%) =
φ
1488 × 2^2n–1 × B × (N + 1)
× 10⁶ – 1
× 100
Rev. 3.00 Mar 21, 2006 page 509 of 814
REJ09B0302-0300