HD6473032F16 Datasheet, PDF (642/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 19 Clock Pulse Generator
External Clock: The external clock frequency should be equal to the system clock frequency (φ)
when not divided by the on-chip frequency divider. Table 19.3 shows the clock timing, and figure
19.6 shows the external clock input timing. Figure 19.7 shows the external clock output
stabilization delay timing.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t_DEXT) has passed after the clock input. The system
must remain reset with the reset signal low during t_DEXT, while the clock output is unstable.
Table 19.3 Clock Timing
VCC = 5.0 V ± 10%
VCC = 3.0V to 3.6V
Item
Symbol Min
Max
External clock input low tEXL
15
—
pulse width
External clock input high tEXH
15
—
pulse width
External clock rise time
tEXr
—
5
External clock fall time
tEXf
—
5
Clock low pulse width
tCL
0.4
0.6
80
—
Clock high pulse width
tCH
0.4
0.6
80
—
External clock output
tDEXT^* 500
—
settling delay time
Note: * tDEXT includes 10 tcyc of RES pulse width (tRESW).
Unit Test Conditions
ns Figure 19.6
ns
ns
ns
tcyc φ ≥ 5 MHz Figure 21.4
ns φ < 5 MHz
tcyc
φ ≥ 5 MHz
ns φ < 5 MHz
µs Figure 19.7
EXTAL
t_EXH
t_EXr
t_EXL
V_CC × 0.7
0.3 V
t_EXf
Figure 19.6 External Clock Input Timing
Rev. 3.00 Mar 21, 2006 page 612 of 814
REJ09B0302-0300
V_CC × 0.5