HD6473032F16 Datasheet, PDF (377/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
• Output compare timing
The compare match signal is generated in the last state in which TCNT and the general register
match (when TCNT changes from the matching value to the next value). When the compare
match signal is generated, the output value selected in TIOR is output at the output compare
pin (TIOCA or TIOCB). When TCNT matches a general register, the compare match signal is
not generated until the next counter clock pulse.
Figure 10.22 shows the output compare timing.
φ
TCNT input
clock
TCNT
N
N+1
GR
N
Compare
match signal
TIOCA,
TIOCB
Figure 10.22 Output Compare Timing
Input Capture Function: The TCNT value can be captured into a general register when a
transition occurs at an input capture/output compare pin (TIOCA or TIOCB). Capture can take
place on the rising edge, falling edge, or both edges. The input capture function can be used to
measure pulse width or period.
• Sample setup procedure for input capture
Figure 10.23 shows a sample procedure for setting up input capture.
Rev. 3.00 Mar 21, 2006 page 347 of 814
REJ09B0302-0300