HD6473032F16 Datasheet, PDF (835/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix D Pin States
Reset in T₂ State: Figure D.2 is a timing diagram for the case in which RES goes low during the
T₂ state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance
state. The address bus is initialized to the low output level 0.5 state after the low level of RES is
sampled. The same timing applies when a reset occurs during a wait state (T_W).
Access to external address
T₁
T₂
T₃
φ
RES
Internal
reset signal
Address bus
H'000000
CS₀
CS₇ to CS₁
AS
High impedance
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
High impedance
High impedance
Figure D.2 Reset during Memory Access (Reset during T₂ State)
Rev. 3.00 Mar 21, 2006 page 805 of 814
REJ09B0302-0300