HD6473032F16 Datasheet, PDF (354/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
Bit 3—Master Enable TIOCB3 (EB3): Enables or disables ITU output at pin TIOCB₃.
Bit 3: EB3
0
1
Description
TIOCB3 output is disabled regardless of TIOR3 and TFCR settings (TIOCB3
operates as a generic input/output pin).
If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
TIOCB3 is enabled for output according to TIOR3 and TFCR settings
(Initial value)
Bit 2—Master Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB₄.
Bit 2: EB4
0
1
Description
TIOCB4 output is disabled regardless of TIOR4 and TFCR settings (TIOCB4
operates as a generic input/output pin).
If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.
TIOCB4 is enabled for output according to TIOR4 and TFCR settings
(Initial value)
Bit 1—Master Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA₄.
Bit 1: EA4
0
1
Description
TIOCA4 output is disabled regardless of TIOR4, TMDR, and TFCR settings
(TIOCA4 operates as a generic input/output pin).
If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1.
TIOCA4 is enabled for output according to TIOR4, TMDR, and TFCR settings
(Initial value)
Bit 0—Master Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA₃.
Bit 0: EA3
0
1
Description
TIOCA3 output is disabled regardless of TIOR3, TMDR, and TFCR settings
(TIOCA3 operates as a generic input/output pin).
If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1.
TIOCA3 is enabled for output according to TIOR3, TMDR, and TFCR settings
(Initial value)
Rev. 3.00 Mar 21, 2006 page 324 of 814
REJ09B0302-0300