HD6473032F16 Datasheet, PDF (446/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 11 Programmable Timing Pattern Controller
Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows
an example in which the TPC is used for cyclic five-phase pulse output.
TCNT value
GRA
TCNT
Compare match
H'0000
NDRB 80
Time
C0 40 60 20 30 10 18 08 88 80 C0 40
PBDR 00 80 C0 40 60 20 30 10 18 08 88 80 C0
TP₁₅
TP₁₄
TP₁₃
TP₁₂
TP₁₁
1. The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare
register and the counter will be cleared by compare match A. The trigger period is set in GRA. The IMIEA bit
is set to 1 in TIER to enable the compare match A interrupt.
2. H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger. Output data H'80 is
written in NDRB.
3. The timer counter in this ITU channel is started. When compare match A occurs, the NDRB contents are
transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt service routine writes
the next output data (H'C0) in NDRB.
4. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing H'40,
H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts. If the DMAC is set for activation by
this interrupt, pulse output can be obtained without loading the CPU.
Figure 11.5 Normal TPC Output Example (Five-Phase Pulse Output)
Rev. 3.00 Mar 21, 2006 page 416 of 814
REJ09B0302-0300