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HD6473032F16 Datasheet, PDF (314/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
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Section 9 I/O Ports
Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores output data for pins PA7 to PA0. When a bit
in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned. When
a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read.
Bit
Initial value
Read/Write
7
PA 7
0
R/W
6
5
4
3
2
1
0
PA 6
PA 5
PA 4
PA 3
PA 2
PA 1
PA 0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
Port A data 7 to 0
These bits store data for port A pins
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 3.00 Mar 21, 2006 page 284 of 814
REJ09B0302-0300
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