HD6473032F16 Datasheet, PDF (204/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 7 Refresh Controller
φ
Address
bus
CS₃
RD
High
HWR
LWR
RFSH
Software standby mode
Oscillator
settling time
High-impedance
High-impedance
High-impedance
High-impedance
Figure 7.16 Signal Output Timing in Self-Refresh Mode (PSRAME = 1, DRAME = 0)
Operation in Power-Down State: The refresh controller operates in sleep mode. It does not
operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR,
RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby
mode.
Example: Pseudo-static RAM may have separate OE and RFSH pins, or these may be combined
into a single OE/RFSH pin. Figure 7.17 shows an example of a circuit for generating an OE/RFSH
signal. Check the device characteristics carefully, and design a circuit that fits them. Figure 7.18
shows a setup procedure to be followed by a program.
H8/3052BF
RD
RFSH
PSRAM
OE / RFSH
Figure 7.17 Interconnection to Pseudo-Static RAM with OE/RFSH Signal (Example)
Rev. 3.00 Mar 21, 2006 page 174 of 814
REJ09B0302-0300