HD6473032F16 Datasheet, PDF (459/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit 6—Reserved: Do not set to 1.
Bits 5 to 0—Reserved: Read-only bits, always read as 1.
Section 12 Watchdog Timer
12.2.4 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte instructions. Figure 12.2 shows the format of data written to TCNT
and TCSR. TCNT and TCSR both have the same write address. The write data must be contained
in the lower byte of the written word. The upper byte must contain H'5A (password for TCNT) or
H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT or TCSR.
TCNT write
Address
15
H'FFA8 *
H'5A
87
0
Write data
TCSR write
Address
15
H'FFA8 *
H'A5
87
0
Write data
Note: * Lower 16 bits of the address.
Figure 12.2 Format of Data Written to TCNT and TCSR
Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be
written by byte transfer instructions. Figure 12.3 shows the format of data written to RSTCSR. To
write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower
byte. The H'00 in the lower byte clears the WRST bit in RSTCSR to 0.
Writing 0 in WRST bit
15
87
0
Address H'FFAA*
H'A5
H'00
Note: * Lower 16 bits of the address.
Figure 12.3 Format of Data Written to RSTCSR
Rev. 3.00 Mar 21, 2006 page 429 of 814
REJ09B0302-0300