HD6473032F16 Datasheet, PDF (643/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 19 Clock Pulse Generator
V_CC 2.7 V
STBY
V_IH
EXTAL
φ (internal or
external)
RES
t_DEXT*
Note: * t_DEXT includes 10 t_cyc of RES pulse width (t_RESW).
Figure 19.7 External Clock Output Settling Delay Timing
19.3 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the signal that becomes the system clock.
19.4 Prescalers
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
19.5 Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
Rev. 3.00 Mar 21, 2006 page 613 of 814
REJ09B0302-0300