HD6473032F16 Datasheet, PDF (434/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 11 Programmable Timing Pattern Controller
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5
and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7
to 4 of address H'FFA7 are reserved bits that cannot be modified and are always read as 1.
Address H'FFA5
Bit
7
6
5
4
3
2
1
0
NDR7 NDR6 NDR5 NDR4 —
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Address H'FFA7
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Reserved bits
Bit
7
6
5
4
3
2
1
0
—
—
—
— NDR3 NDR2 NDR1 NDR0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W R/W
Reserved bits
Next data 3 to 0
These bits store the next output
data for TPC output group 0
Rev. 3.00 Mar 21, 2006 page 404 of 814
REJ09B0302-0300