HD6473032F16 Datasheet, PDF (450/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 11 Programmable Timing Pattern Controller
11.4 Usage Notes
11.4.1 Operation of TPC Output Pins
TP₀ to TP₁₅ are multiplexed with ITU, DMAC, address bus, and other pin functions. When ITU,
DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output. The
data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
11.4.2 Note on Non-Overlapping Output
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as
follows.
1. NDR bits are always transferred to DR bits at compare match A.
2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 11.9 illustrates the non-overlapping TPC output operation.
DDR
Q
NDER
Q
Compare match A
Compare match B
TPC output pin
C
Q DR D
Q NDR D
Figure 11.9 Non-Overlapping TPC Output
Internal
data bus
Rev. 3.00 Mar 21, 2006 page 420 of 814
REJ09B0302-0300