HD6473032F16 Datasheet, PDF (134/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 5 Interrupt Controller
5.5 Usage Notes
5.5.1 Contention between Interrupt Generation and Disabling
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
actually disabled until after execution of the instruction is completed. Thus, if an interrupt occurs
while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at
the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt
exception handling is carried out. If a higher-priority interrupt is also requested, however,
interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority
interrupt is ignored. This also applies when an interrupt source flag is cleared to 0.
Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in TIER of the ITU.
TIER write cycle by CPU
IMIA exception handling
φ
Internal
address bus
Internal
write signal
IMIEA
TIER address
IMIA
IMFA interrupt
signal
Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction
This type of contention will not occur if the interrupt is masked when the interrupt enable bit or
flag is cleared to 0.
Rev. 3.00 Mar 21, 2006 page 104 of 814
REJ09B0302-0300