HD6473032F16 Datasheet, PDF (178/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 7 Refresh Controller
7.1.3 Pin Configuration
Table 7.1 summarizes the refresh controller’s input/output pins.
Table 7.1 Refresh Controller Pins
Pin
Name
RFSH Refresh
Signal
Abbr.
RFSH
I/O
Output
HWR
LWR
RD
CS3
Upper write/upper column
address strobe
Lower write/lower column
address strobe
Column address strobe/
write enable
Row address strobe
UW/UCAS
LW/LCAS
CAS/WE
RAS
Output
Output
Output
Output
Function
Goes low during refresh cycles;
used to refresh DRAM and PSRAM
Connects to the UW pin of 2WE
DRAM or UCAS pin of 2CAS DRAM
Connects to the LW pin of 2WE
DRAM or LCAS pin of 2CAS DRAM
Connects to the CAS pin of 2WE
DRAM or WE pin of 2CAS DRAM
Connects to the RAS pin of DRAM
7.1.4 Register Configuration
Table 7.2 summarizes the refresh controller’s registers.
Table 7.2 Refresh Controller Registers
Address^* Name
H'FFAC
Refresh control register
H'FFAD
Refresh timer control/status register
H'FFAE
Refresh timer counter
H'FFAF
Refresh time constant register
Note: * Lower 16 bits of the address.
Abbreviation R/W
RFSHCR
R/W
RTMCSR
R/W
RTCNT
R/W
RTCOR
R/W
Initial Value
H'02
H'07
H'00
H'FF
Rev. 3.00 Mar 21, 2006 page 148 of 814
REJ09B0302-0300