HD6473032F16 Datasheet, PDF (408/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
10.5 Interrupts
The ITU has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
10.5.1 Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a
compare match signal generated when TCNT matches a general register (GR). The compare match
signal is generated in the last state in which the values match (when TCNT is updated from the
matching count to the next count). Therefore, when TCNT matches a general register, the compare
match signal is not generated until the next timer clock input. Figure 10.57 shows the timing of the
setting of IMFA and IMFB.
φ
TCNT input
clock
TCNT
N
N+1
GR
N
Compare
match signal
IMF
IMI
Figure 10.57 Timing of Setting of IMFA and IMFB by Compare Match
Rev. 3.00 Mar 21, 2006 page 378 of 814
REJ09B0302-0300