HD6473032F16 Datasheet, PDF (460/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 12 Watchdog Timer
Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Byte access
instructions can be used. The read addresses are H'FFA8 for TCSR, H'FFA9 for TCNT, and
H'FFAB for RSTCSR, as listed in table 12.2.
Table 12.2 Read Addresses of TCNT, TCSR, and RSTCSR
Address^*
Register
H'FFA8
TCSR
H'FFA9
TCNT
H'FFAB
RSTCSR
Note: * Lower 16 bits of the address.
12.3 Operation
Operations when the WDT is used as a watchdog timer and as an interval timer are described
below.
12.3.1 Watchdog Timer Operation
Figure 12.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and
overflows due to a system crash etc., the chip is internally reset for a duration of 518 states.
A reset generated by the WDT has the same vector as a reset generated by input at the RES pin.
Software can distinguish a RES reset from a watchdog reset by checking the WRST bit in
RSTCSR.
If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.
Rev. 3.00 Mar 21, 2006 page 430 of 814
REJ09B0302-0300