HD6473032F16 Datasheet, PDF (200/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 7 Refresh Controller
Example 4: Connection to Multiple 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7.13
shows an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the corresponding
address map. Up to four DRAM chips can be connected to area 3 by decoding upper address bits
A₁₉ and A₂₀.
Figure 7.14 shows a setup procedure to be followed by a program for this example. The DRAM in
this example has 9-bit row addresses and 9-bit column addresses. Both chips must be refreshed
simultaneously, so the RFSH pin must be used.
H8/3052BF
A ₁₉
A ₉ to A ₁
2 CAS 4-Mbit DRAM with 9-bit
row address, 9-bit column
address, and × 16-bit organization
A₈ to A ₀
RAS
UCAS
LCAS
WE
OE
I/O₁₅ to I/O₀
No. 1
CS ₃
HWR
LWR
RD
A₈ to A ₀
RAS
UCAS
LCAS
WE
No. 2
RFSH
D₁₅ to D ₀
OE
I/O₁₅ to I/O₀
a. Interconnections (example)
H'600000
H'67FFFF
H'680000
H'6FFFFF
H'700000
No. 1
DRAM area
No. 2
DRAM area
Area 3 (16-Mbyte mode)
Not used
H'7FFFFF
b. Address map
Figure 7.13 Interconnections and Address Map for Multiple 2CAS 4-Mbit DRAM Chips
(Example)
Rev. 3.00 Mar 21, 2006 page 170 of 814
REJ09B0302-0300