HD6473032F16 Datasheet, PDF (660/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 20 Power-Down State
MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be accessed
from the CPU. It can be read by the DMAC, but it cannot be written by the DMAC.
20.7 System Clock Output Disabling Function
Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCR. When the PSTOP
bit is set to 1, output of the system clock halts and the φ pin is placed in the high-impedance state.
Figure 20.3 shows the timing of the stopping and starting of system clock output. When the
PSTOP bit is cleared to 0, output of the system clock is enabled. Table 20.4 indicates the state of
the φ pin in various operating states.
MSTCR write cycle
(PSTOP = 1)
MSTCR write cycle
(PSTOP = 0)
φ pin
T1 T2 T3
High impedance
T1 T2 T3
Figure 20.3 Starting and Stopping of System Clock Output
Table 20.4 φ Pin State in Various Operating States
Operating State
Hardware standby
Software standby
Sleep mode
Normal operation
PSTOP = 0
High impedance
Always high
System clock output
System clock output
PSTOP = 1
High impedance
High impedance
High impedance
High impedance
Rev. 3.00 Mar 21, 2006 page 630 of 814
REJ09B0302-0300