HD6473032F16 Datasheet, PDF (146/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 6 Bus Controller
6.2.5 Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables address output on bus lines A₂₃ to A₂₁ and
enables or disables release of the bus to an external device.
Bit
7
6
5
4
3
2
1
0
A23E A22E A21E
—
—
—
—
BRLE
Initial value
1
1
1
1
1
1
1
0
Read/ ^{Modes 1, 2, 5, 7 —}
—
—
—
—
—
—
R/W
Write _{Modes 3, 4, 6 R/W}
R/W
R/W
—
—
—
—
R/W
Address 23 to 21 enable
These bits enable PA ₆ to
PA ₄ to be used for A ₂₃ to
A ₂₁ address output
Reserved bits
Bus release enable
Enables or disables
release of the bus to
an external device
BRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA₄ to be used as the A₂₃ address output pin.
Writing 0 in this bit enables A₂₃ address output from PA₄. In modes other than 3, 4, and 6 this bit
cannot be modified and PA₄ has its ordinary input/output functions.
Bit 7: A23E
0
1
Description
PA4 is the A23 address output pin
PA4 is the PA4/TP4/TIOCA1 input/output pin
(Initial value)
Bit 6—Address 22 Enable (A22E): Enables PA₅ to be used as the A₂₂ address output pin.
Writing 0 in this bit enables A₂₂ address output from PA₅. In modes other than 3, 4, and 6 this bit
cannot be modified and PA₅ has its ordinary input/output functions.
Bit 6: A22E
0
1
Description
PA5 is the A22 address output pin
PA5 is the PA5/TP5/TIOCB1 input/output pin
(Initial value)
Rev. 3.00 Mar 21, 2006 page 116 of 814
REJ09B0302-0300