HD6473032F16 Datasheet, PDF (622/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 18 ROM
Table 18.10 Hardware Protection
Functions
Item
Description
Program Erase Verify^*1
FWE pin
protection
Reset/
standby
protection
• When a low level is input to the FWE pin,
FLMCR1, FLMCR2, (except bit FLER) EBR1,
No^*2
and EBR2 are initialized, and the program/
erase-protected state is entered.^*5
• In a power-on reset (including a WDT power-on No
reset) and in standby mode, FLMCR1, FLMCR2,
EBR1, and EBR2 are initialized, and the
program/erase-protected state is entered.
No^*3 —
No^*3 —
• In a reset via the RES pin, the reset state is not
entered unless the RES pin is held low until
oscillation stabilizes after powering on. In the
case of a reset during operation, hold the RES
pin low for the RES pulse width specified in the
AC Characteristics section. ^*6
Error
protection
• When a microcomputer operation error (error
No
generation (FLER=1)) was detected while flash
memory was being programmed/erased, error
protection is enabled. At this time, the FLMCR1,
FLMCR2, EBR1, and EBR2 settings are held, but
programming/erasing is aborted at the time the
error was generated. Error protection is released
only by a reset via the RES pin or a WDT reset,
or in the hardware standby mode.
No^*3 Yes^*4
Notes: 1. Two modes: program-verify and erase-verify.
2. Excluding a RAM area overlapping flash memory.
3. All blocks are unerasable and block-by-block specification is not possible.
4. It is possible to perform a program-verify operation on the 128 bytes being
programmed, or an erase-verify operation on the block being erased.
5. For details see section 18.11, Flash Memory Programming and Erasing Precautions.
6. See section 4.2.2, Reset Sequence, and section 18.11, Flash Memory Programming
and Erasing Precautions. The H8/3052BF requires at least 20 system clocks for a reset
during operation.
Rev. 3.00 Mar 21, 2006 page 592 of 814
REJ09B0302-0300