HD6473032F16 Datasheet, PDF (185/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7.3 Operation
Section 7 Refresh Controller
7.3.1 Overview
One of three functions can be selected for the H8/3052BF refresh controller: interfacing to DRAM
connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval timing.
Table 7.3 summarizes the register settings when these three functions are used.
Table 7.3 Refresh Controller Settings
Register Settings
RFSHCR
SRFMD
PSRAME
DRAME
CAS/WE
M9/M8
RFSHE
RCYCE
RTCOR
RTMCSR
CKS2 to
CKS0
CMF
CMIE
P8DDR
ABWCR
P81DDR
ABW3
DRAM Interface
Selects self-refresh
mode
Cleared to 0
Set to 1
Selects 2CAS or
2WE mode
Selects column
addressing mode
Selects RFSH signal
output
Selects insertion of
refresh cycles
Refresh interval
setting
Usage
PSRAM Interface
Selects self-refresh
mode
Set to 1
Cleared to 0
—
—
Selects RFSH signal
output
Selects insertion of
refresh cycles
Refresh interval
setting
Interval Timer
Cleared to 0
Cleared to 0
Cleared to 0
—
—
Cleared to 0
—
Interrupt interval
setting
Set to 1 when
RTCNT = RTCOR
Cleared to 0
Set to 1 (CS3 output)
Cleared to 0
Set to 1 when
RTCNT = RTCOR
Cleared to 0
Set to 1 (CS3 output)
—
Set to 1 when
RTCNT = RTCOR
Enables or disables
interrupt requests
Set to 0 or 1
—
Rev. 3.00 Mar 21, 2006 page 155 of 814
REJ09B0302-0300