HD6473032F16 Datasheet, PDF (623/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 18 ROM
18.8.2 Software Protection
Software protection can be implemented by setting the SWE1 bit in FLMCR1, the SWE2 bit in
FLMCR2, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the
RAM control register (RAMCR). When software protection is in effect, setting the P1 or E1 bit in
flash memory control register 1 (FLMCR1), or the P2 or E2 bit in flash memory control register 2
(FLMCR2) does not cause a transition to program mode or erase mode. (See table 18.11.)
Table 18.11 Software Protection
Item
Description
Functions
Program Erase Verify^*1
Block
specification
protection
• Erase protection can be set for individual
—
blocks by settings in erase block register 1
(EBR1)^*2 and erase block register 2 (EBR2)^*2.
However, programming protection is disabled.
No
Yes
Emulation
protection
• Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
• Setting the RAMS bit to 1 in the RAM
control register (RAMCR) places all blocks
in the program/erase-protected state.
No^*3
No^*4 Yes
Notes: 1. Two modes: program-verify and erase-verify.
2. When not erasing, clear all EBR1, EBR2 bits to H'00.
3. A RAM area overlapping flash memory can be written to.
4. All blocks are unerasable and block-by-block specification is not possible.
Rev. 3.00 Mar 21, 2006 page 593 of 814
REJ09B0302-0300