HD6473032F16 Datasheet, PDF (233/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 DMA Controller
Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3: DTIE
0
1
Description
The DEND interrupt requested by DTE is disabled
The DEND interrupt requested by DTE is enabled
(Initial value)
Bits 2 and 1—Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full
address mode when DTS2A and DTS1A are both set to 1.
Bit 0—Data Transfer Select 0A (DTS0A): Selects normal mode or block transfer mode.
Bit 0: DTS0A
0
1
Description
Normal mode
Block transfer mode
(Initial value)
Operations in these modes are described in sections 8.4.5, Normal Mode, and 8.4.6, Block
Transfer Mode.
DTCRB
Bit
Initial value
Read/Write
7
6
DTME
—
0
0
R/W
R/W
5
DAID
0
R/W
4
DAIDE
0
R/W
3
TMS
0
R/W
2
DTS2B
0
R/W
1
DTS1B
0
R/W
0
DTS0B
0
R/W
Data transfer master enable
Enables or disables data
transfer, together with
the DTE bit, and is cleared
to 0 by an interrupt
Reserved bit
Transfer mode select
Selects whether the
block area is the source
or destination in block
transfer mode
Destination address
increment/decrement
Destination address
increment/decrement enable
These bits select whether
the destination address
register (MARB) is incremented,
decremented, or held fixed
during the data transfer
Data transfer select
2B to 0B
These bits select the data
transfer activation source
DTCRB is initialized to H'00 by a reset and in standby mode.
Rev. 3.00 Mar 21, 2006 page 203 of 814
REJ09B0302-0300