HD6473032F16 Datasheet, PDF (430/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 11 Programmable Timing Pattern Controller
11.1.4 Register Configuration
Table 11.2 summarizes the TPC registers.
Table 11.2 TPC Registers
Address^*1 Name
Abbreviation R/W
Initial Value
H'FFD1
H'FFD3
Port A data direction register
Port A data register
PADDR
PADR
W
R/(W)^*2
H'00
H'00
H'FFD4
H'FFD6
Port B data direction register
Port B data register
PBDDR
PBDR
W
R/(W)^*2
H'00
H'00
H'FFA0
TPC output mode register
TPMR
R/W
H'F0
H'FFA1
TPC output control register
TPCR
R/W
H'FF
H'FFA2
Next data enable register B
NDERB
R/W
H'00
H'FFA3
Next data enable register A
NDERA
R/W
H'00
H'FFA5/
H'FFA7^*3
Next data register A
NDRA
R/W
H'00
H'FFA4
H'FFA6^*3
Next data register B
NDRB
R/W
H'00
Notes: 1. Lower 16 bits of the address.
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFA5 when the same output trigger is selected for TPC output
groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA
address is H'FFA7 for group 0 and H'FFA5 for group 1. Similarly, the address of NDRB
is H'FFA4 when the same output trigger is selected for TPC output groups 2 and 3 by
settings in TPCR. When the output triggers are different, the NDRB address is H'FFA6
for group 2 and H'FFA4 for group 3.
Rev. 3.00 Mar 21, 2006 page 400 of 814
REJ09B0302-0300