HD6473032F16 Datasheet, PDF (351/847 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.4 Timer Function Control Register (TFCR)
TFCR is an 8-bit readable/writable register that selects complementary PWM mode, reset-
synchronized PWM mode, and buffering for channels 3 and 4.
Bit
7
—
Initial value
1
Read/Write
—
6
5
4
3
2
1
0
— CMD1 CMD0 BFB4 BFA4 BFB3 BFA3
1
0
0
0
0
0
0
—
R/W R/W R/W R/W R/W R/W
Reserved bits
Combination mode 1/0
These bits select complementary
PWM mode or reset-synchronized
PWM mode for channels 3 and 4
Buffer mode B4 and A4
These bits select buffering of
general registers (GRB4 and
GRA4) by buffer registers
(BRB4 and BRA4) in channel 4
Buffer mode B3 and A3
These bits select buffering
of general registers (GRB3
and GRA3) by buffer
registers (BRB3 and BRA3)
in channel 3
TFCR is initialized to H'C0 by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels
3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode.
Bit 5: CMD1
0
1
Bit 4: CMD0
0
1
0
1
Description
Channels 3 and 4 operate normally
(Initial value)
Channels 3 and 4 operate together in complementary
PWM mode
Channels 3 and 4 operate together in reset-synchronized
PWM mode
Rev. 3.00 Mar 21, 2006 page 321 of 814
REJ09B0302-0300